(1) Field of the Invention
The present invention relates to a semiconductor device including capacitors and a method for fabricating the same, and more particularly relates to a semiconductor device having concave DRAM (Dynamic Random Access Memory) capacitors and a method for fabricating the same.
(2) Description of Related Art
In recent years, for DRAMs for which increasing miniaturization is demanded, attention has been directed toward a method in which a metal oxide film having a high permittivity, more particularly, a TaOx film, is used as a capacitive insulating film of a capacitor to ensure sufficient charge retention characteristics (see, for example, Japanese Unexamined Patent Publication No. 11-026712).
When a TaOx film is used as a capacitive insulating film and a material having Si as the main ingredient is used as a material of a lower electrode, this can provide a relative permeability of 15 through 20. On the other hand, when a TaOx film is used as a capacitive insulating film and a metal film is used as a lower electrode, this can provide a relative permeability of 50 at the maximum. As described above, a TaOx film used as a capacitive insulating film can have three or more times as large a capacitance in the same capacitor area as a SiO2 film or an ON film (a film obtained by stacking a SiO2 film and a SiNx film) used as a capacitive insulating film.
Furthermore, since a TaOx film can be formed within a low-temperature range of, for example, 400 through 500° C. by thermal chemical vapor deposition (CVD), it is effective also at reducing the thermal damage to other elements.
In general, when a TaOx film is used as a capacitive insulating film, a TiN film, which can be formed of a material containing no organic material that may deteriorate the properties of the capacitive insulating film, is selected as an upper electrode. A TiN film is usually formed of a material having TiCl4 and NH3 as the main ingredients by thermal CVD. Since a TiN film can be formed within a temperature range of 400 through 600° C., the formation of the TiN film will not lead to the deteriorated properties of a TaOx film serving as a capacitive insulating film or other elements, such as transistors.
However, in a DRAM capacitor having a capacitive insulating film of a TaOx film and an upper electrode of a TiN film, the problem that the stress produced in the TiN film is applied to the TaOx film has been caused. This problem will be described below in more detail with reference to the drawings. FIG. 5A is a cross-sectional view showing a schematic structure of a known semiconductor device including DRAM capacitors.
As shown in FIG. 5A, the semiconductor device includes a first interlayer insulating film 101, a plurality of lower electrodes 103 of a silicon film formed on the entire surfaces of a plurality of trenches 102 formed in the first interlayer insulating film 101, a capacitive insulating film 104 of a TaOx film formed to cover the entire surfaces of the lower electrodes 103, an upper electrode 105 of a TiN film partly covering the capacitive insulating film 104, and a second interlayer insulating film 106 covering the upper electrode 105. Each of known DRAM capacitors 100 is formed of one of the lower electrodes 103, the capacitive insulating film 104 and the upper electrode 105. The capacitive insulating film 104 and the upper electrode 105 are formed to cover the entire surfaces of the plurality of trenches 102 and the first interlayer insulating film 101 located outside the trenches 102.
FIG. 5B is an enlarged cross-sectional view showing a part of the structure of the semiconductor device shown in FIG. 5A in which the capacitive insulating film 104 and the upper electrode 105 are successively stacked on the first interlayer insulating film 101, i.e., a part thereof surrounded by broken lines in FIG. 5A. As shown in FIG. 5B, the first interlayer insulating film 101, the capacitive insulating film 104 and the upper electrode 105 are successively stacked to make contact with one another.
FIG. 5C is a plan view showing a schematic structure of a DRAM array region in which a plurality of DRAM capacitors 100 are arranged. As shown in FIG. 5C, the DRAM capacitors 100 are arranged in a matrix of rows and columns. For example, several 10 k through 1 G capacitors are arranged in a single array. In this structure, an upper electrode 105 is formed to cover a plurality of trenches 102 and have a large area. The formation of such a large-area upper electrode 105 increases the stress of the upper electrode 105 itself, leading to stress concentration at a specific DRAM capacitor.
FIG. 5D is a diagram showing the state of the stress applied to a DRAM capacitor 100 and its vicinity. As shown in FIG. 5D, the stress concentrates, in particular, at part of the upper electrode 105 covering the first interlayer insulating film 101 located outside the trenches 102. When this stress reaches the capacitive insulating film 104, the capacitive insulating film 104 is deteriorated in its leakage current characteristics and charge retention characteristics. Such deterioration in initial characteristics, such as the leakage current characteristics and the charge retention characteristics, facilitates an electrical breakdown, leading to the reduced long-term reliability.